High-speed multiplier having carry-save adder circuit

Details High-speed multiplier having carry-save adder circuit High-speed multiplier having carry-save adder circuit

1985-11-06

1988-06-21

Harkcom, Gary V.

Boots, shoes, and leggings

364757, 364784, 364754, G06F 752, G05F 750

Patent

active

047529059

ABSTRACT:
A high-speed multiplier adapted to VLSI with a regularly arranged structure having a reduced number of addition stages. There is provided a carry save adder circuit wherein a time difference is imparted to signals input to full adders, in order to eliminate extra wait time in the signal propagation. That is, a carry signal of a full adder of two stages over is input with a speed increase of 1/2T.sub.FA.

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J. Iwamura et al., "A CMOS/SOS Multiplier", IEEE ISSCC Digest of Technical Papers, Feb. 1984, pp. 92-93.
M. Mano, "Computer System Architecture", Prentice-Hall, Inc., 1982, pp. 18-21.
D. Agrawal, "High-Speed Arithmetic Arrays", IEEE Trans. on Computers, vol. C-28, No. 3, Mar. 1979, pp. 215-224.

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