Process for fabricating a BiCMOS integrated circuit

Fishing – trapping – and vermin destroying

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437 28, 437 56, 437 59, 148DIG9, H01L 21265

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active

051242710

ABSTRACT:
A process and structure for resolving the divergent etching requirements of a relatively thick base oxide (62) and a relatively thin gate oxide (64) in a BiCMOS integrated circuit. The necessity of etching base oxide (62) is eliminated by extending nitride mask (58) over the extrinsic base region (86) so that the relatively thick base oxide (62) only covers intrinsic base region (60) and tab region (61). Base oxide (62) at tab region (61) is partially etched in the course of forming sidewall oxide filaments (78), resulting in the residual tab oxide (62'). An extrinsic base implant is performed in extrinsic base region (86) and tab region (61), with the presence of residual tab oxide (62') affecting the profile of the implant so that it is stepped. The resulting structure, after an anneal, is extrinsic base (87'), an intrinsic base (63) (formed prior to the extrinsic base implant), and an overlap region (88') common to both. Extrinsic base ( 87') has a relatively greater dopant concentration compared to intrinsic base region (63). The dopant concentration in overlap region (88') is substantially that of extrinsic base (87'). The overlap region (88') insures adequate conductivity link-up between the extrinsic base (87') and the intrinsic base (63). Since no thick base oxide (62) is ever formed in extrinsic base region (86), no undesirable heavy etch is required in extrinsic base region (86), such a heavy etch being undesirable because of the necessity of an extra processing step for masking areas containing the relatively thinner oxide (64). Thus, a processing step is eliminated and yet adequate conductivity link-up between extrinsic base (87') and intrinsic base (63) is achieved via overlap region (88').

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