Method of manufacturing flat panel backplanes, display transisto

Details Method of manufacturing flat panel backplanes, display transisto Method of manufacturing flat panel backplanes, display transisto

1990-01-16

1992-06-23

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

148DIG105, 437 50, 437l51, 437181, 437192, 437962, H01L 21265

Patent

active

051238470

ABSTRACT:
An improved method of manufacturing active matrix display backplanes with thin film transistors thereon and a drive scheme therefor. A refractory metal covers the indium tin oxide (ITO) layer, patterned to form a gate electrode for the transistors and to protect the pixel pad ITO during formation of the transistors. To reduce shorts and capacitance between the gate and the source or the drain, an intermetal dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges.

REFERENCES:
patent: 4545112 (1985-10-01), Holmberg et al.
patent: 4563806 (1986-01-01), Coissard et al.
patent: 4601097 (1986-07-01), Shimbo
patent: 4624737 (1986-11-01), Shimbo
patent: 4680085 (1987-07-01), Vijan et al.
patent: 4697331 (1987-10-01), Boulitrop et al.
patent: 4732873 (1988-03-01), Perbet et al.
patent: 4735822 (1988-04-01), Ohtoshi et al.
patent: 4736229 (1988-04-01), Holmberg et al.
patent: 4736234 (1988-04-01), Boulitrop et al.

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