Arrangement for testing digital circuit devices having tri-state

Details Arrangement for testing digital circuit devices having tri-state Arrangement for testing digital circuit devices having tri-state

1990-12-26

1992-11-24

Canney, Vincent P.

Excavating

371 221, G01R 3128

Patent

active

051669374

ABSTRACT:
An arrangement is disclosed that is added to digital circuit device for providing a way of easily verifying that the device's input and output circuits are operating and connected properly. The arrangement implements a test mode in which a simple exercising sequence is placed on any single input of a defined sequential group of device pins. A resultant output can be observed on the next occurring output and all subsequent outputs of the defined sequential group.

REFERENCES:
patent: 4583223 (1986-04-01), Inoue et al.

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