Input-weighted transversal filter

Details Input-weighted transversal filter Input-weighted transversal filter

1991-06-28

1992-11-24

Mai, Tan V.

Boots, shoes, and leggings

364758, G06F 1531, G06F 752

Patent

active

051668955

ABSTRACT:
Tap arithmetic units and first delay circuits are arranged alternately. Each of the tap arithmetic units has a full-adder array for multiplying an input signal which has been sampled at regular intervals and coefficients, a second pipeline delay circuit for delaying outputs of the full-adder array by a predetermined time and an adder circuit for adding outputs of the second delay circuits. The first and second delay circuits are timed to the preceding tap arithmetic unit for arithmetic operations. The use of the second delay circuit for the timing of arithmetic operations permits the arrangement of the first delay circuit to be simplified.

REFERENCES:
patent: 4594678 (1986-06-01), Uhlenhoff
IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 92-93, 1984.

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