Boots – shoes – and leggings
Patent
1993-02-05
1994-12-27
Malzahn, David H.
Boots, shoes, and leggings
G06F 752
Patent
active
053771354
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a high cardinal number type non-restoring divider and more specifically to a divider or a floating point type coprocessor or vector processor including a divider.
FIELD OF THE INVENTION
Division is generally considered, in conceptually, as an inverse processing of multiplication, but different, in many respects, from multiplication. First, prior- and post-processing are not independent, and are conducted sequentially. With division, since all partial products can be obtained simultaneously, processing is not conducted sequentially and, therefore, extra arithmetic cycles are required for divisions, in comparison with multiplication. Second, division is not deterministic processing but is trial-and-error processing. That is, a predicted processing of a partial quotient is required in the process of repetitive arithmetic operations. For example, a digit selection rule for selecting each digit of a series of quotients from an aggregation of digits is used.
FIG. 1 is an block diagram of a conventional divider, showing an example of a high cardinal number non-restoring divider. Here, the system of division can be classified into restoring division and non-restoring division from the difference of digit aggregation. Restoring division is essentially the same as division by a manual arithmetic operation and can easily be realized, but sometimes requires a longer execution time if a large number of zeroes exists within the digits of the quotient. It is because processing, including addition, for restoring a partial remainder is also required if a negative partial remainder exits. Meanwhile, non- restoring division is not required to restore a negative remainder to a positive remainder, so long as an absolute value of the remainder is smaller than the divisor and is superior to the point that such extra addition is not required. Such a division method is explained, for example, in the "Computer Arithmetic PRINCIPLES, ARCHITECTURE, AND DESIGN" Kai Hwang, issued by John Wiley & Sons, Inc., Chapter 7 or in the Japanese Patent Laid-Open No. 61-7939 (Laid-Open Date: Jan. 14, 1986, "HIGH CARDINAL NUMBER TYPE NON-RESTORING DIVIDER").
A high cardinal number type non-restoring divider uses a cardinal number which is larger than 2 (high cardinal number) and can quickly reduce the number of repetitive processings which are required for execution of the division instruction, with an increase of the cardinal number. Thereby, the execution time is reduced.
In FIG. 1, the reference numeral 1 denotes a divisor register; 2, a dividend register; 3, a multiple generator; 2, an adder/subtractor; 5, a complement generator; 6, a quotient predicting unit; 7, a quotient compensating unit; 8, a quotient register. Only one quotient predicting unit 6, corresponding to a positive or negative partial remainder, is shown to reduce the circuit scale shown in FIG. 1.
A general flow of arithmetic processing is as follow: 1 content of the divisor register 1 (DSR) is multiplied by m (m is a multiple generated in the multiple generator 3), 2 m.times.DSR and content (PR) of the dividend register 2 are added, 3 either the significant n-bits (hereinafter, preferentially n=5) of the addition result, excluding the sign bit, or an output of the complement converting circuit 5b (obtained by complement conversion of the significant 5 bits, excluding the sign bit of the addition result) is given to a decoder 5c (the detail of the structure will be explained in the "DESCRIPTION OF THE PREFERRED EMBODIMENTS" Section. For example, when the sign bit is 0, meaning that the sign is positive, the 5 bits of the addition result are provided directly to the decoder 5c, and when the sign bit is 1, meaning that the sign is negative, the complement of the 5 bits of the addition result are provided to the decoder 5c. A series of operations for generating a quotient predicting signal, based on the an output of the decoder 5c and contents of dividend register 1, are repeated for each digit to determine a partial quot
REFERENCES:
patent: 4722069 (1988-01-01), Ikeda
patent: 5031138 (1991-07-01), Maass et al.
IBM Technical Disclosure Bulletin, vol. 30, No. 6, Nov. 1987, Armonk, NY, "Radix 16 Divider," pp. 415-419.
Fujitsu Limited
Malzahn David H.
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