System for enhanced implementation of add-compare-select (ACS) f

Details System for enhanced implementation of add-compare-select (ACS) f System for enhanced implementation of add-compare-select (ACS) f

1992-04-07

1994-12-27

Mai, Tan V.

Boots, shoes, and leggings

G06F 738

Patent

active

053771338

ABSTRACT:
An improved system and method is provided for enhanced add-compare-select (ACS) implementation which is particularly adapted to time-nesting or over-lapping of the time offsets for add and compare operations. The compare operation is implemented as a sequential bottom-up procedure whereby two numerical quantities are compared by first declaring one of the quantities as a "contingent" smaller or larger quantity. Subsequently, the least significant bits LSBs of the quantities are compared and the earlier contingent designation is retained unless the smaller of the compared bits is found to correspond to the quantity not previously designated as the "contingent" smaller quantity, whereupon the "contingent" designation is transferred to the previously un-designated quantity corresponding to the smaller of the compared bits. The process is iterated until all bit pairs in the compared quantities have been examined and the "contingent" smaller quantity remaining at that point is defined to be the "final" smaller quantity and constitutes the result of the overall compare operation. The enhanced ACS implementation compresses the computation time by almost a factor of two compared to traditional ACS implementations using top-down compare operations, without significantly affecting logic complexity of the system and eliminates the need for tie breaking.

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