Random access memory system providing high-speed digital data ou

Details Random access memory system providing high-speed digital data ou Random access memory system providing high-speed digital data ou

1977-02-01

1978-08-08

Konick, Bernard

Static information storage and retrieval

Addressing

Byte or page addressing

365221, G11C 802, G11C 700

Patent

active

041061098

ABSTRACT:
The disclosed random access memory (RAM) for digital data includes the normal data input circuit, a memory matrix for storing applied data, address control circuits for selectively addressing any cell of the memory matrix, and a data output circuit for selectively applying digital data stored in the memory matrix to a data output line. To achieve a high digital data output rate, a rate substantially higher than the rate at which the cells of the memory can be addressed, the improved RAM includes a data output register having a multiplicity of data storage elements and means for simultaneously reading digital data stored in the memory matrix in parallel into the data storage elements of the output register. This data then is selectively applied to the data output line while new data is being addressed in the memory matrix. Thus, data may be accessed in the memory matrix of the RAM at the normal, relatively slow rate while data previously loaded into the output register is read to the data output line at a relatively high rate.

REFERENCES:
patent: 3317902 (1967-05-01), Michael
patent: 3641519 (1972-02-01), Ashley
patent: 3691538 (1972-04-01), Haney et al.
patent: 3898632 (1975-08-01), Spencer, Jr.
patent: 3992703 (1976-11-01), Luisi et al.
patent: 4023144 (1977-05-01), Koenig

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