Signal delay system

Details Signal delay system Signal delay system

1977-06-21

1979-03-06

Heyman, John S.

Registers

Coded record sensors

Particular sensor structure

328 37, 328 48, 235 92SH, H03K 5159, H03K 2136

Patent

active

041433262

ABSTRACT:
An apparatus for delaying a signal n period lengths by the use of two shift registers which have capacities less than n but which have a total capacity greater than n. The signal to be delayed is fed to a first shift register until that shift register is full. The signal is then fed to a second shift register. Timing signals which control the shift registers' receipt of information are properly blanked in order to allow this result. When n bits of information have been recorded by the shift registers, the first shift register is again inputted causing an output which corresponds to the first data bits of the signal. While the first shift register is receiving and outputting the second cycle of information a pre-determined number of data bits are fed to the second shift register to fill the register. This cycle is repeated resulting in the storage of n data bits by a plurality of shift registers which each have a capacity less than n which have a total capacity greater than n.

REFERENCES:
patent: 3044065 (1962-07-01), Barney et al.
patent: 3096483 (1963-07-01), Ransom
patent: 3588707 (1971-06-01), Manship
patent: 3675049 (1972-07-01), Haven
patent: 3851154 (1974-11-01), Beecham
patent: 3941982 (1976-03-01), Knollenberg et al.

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