Method and apparatus for clocking variable pixel frequencies and

Details Method and apparatus for clocking variable pixel frequencies and Method and apparatus for clocking variable pixel frequencies and

1992-08-11

1996-03-26

Lee, Thomas C.

Boots, shoes, and leggings

395162, 364270, 364DIG1, 364926, 3649272, 364DIG2, G09G 128, G06F 112, G06F 104

Patent

active

055028373

ABSTRACT:
A method and apparatus for synchronizing pixel data flow within a memory display interface (MDI) to enable variable pixel depths, and to support display devices requiring differing pixel rates. A clock circuit receives a pixel clock from a DAC, and generates a shift clock (VSCLK), a pipeline clock, and an input control signal, all of which are synchronized to the pixel clock. The pixel clock synchronizes color pixel data transfer from the MDI to the DAC. The pipeline clock synchronizes pixel data processing through a pixel processing pipeline according to the frequency of the pixel clock and the number of pixels processed in parallel through the pixel processing pipeline. The input control signal feeds the pixel data from a VRAM frame buffer into the pixel processing pipeline according to the pixel depth mode, the frequency of the pixel clock, and the number of pixels processed in parallel through the pixel processing pipeline. The VSCLK controls pixel data transfer from the VRAM frame buffer over the video bus according to the pixel depth mode and the frequency of the pixel clock.

REFERENCES:
patent: 5371517 (1994-12-01), Izzi et al.
Birman et al., IEEE 1991 Custom Integrated Circuts Conference, "100 Mpixel/sec single-chip integrated graphics controller (IGC)", pp. 16.5.1-16.5.4.
Schnaitter et al., IEEE 1991 Custom Integrated Circuts Conference, "170 Mhz CMOS Pixel Processor for Windowing Graphics", pp. 16.6.1-16.6.4.
Leonard et al., IEEE Journal of Solid-State Circuits, "A 66-MHz DSP-augmented RAMDAC for Smooth-Shaded Graphic Applications", v. 26 No. 3 1991, pp. 217-228.
Gutierrez et al., IEEE 1990 Custom Integrated Circuts Conference, "An Integrated PLL Clock Generator for 275 MHz Graphic Displays", pp. 15.1.1-15.1.4.

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