Excavating
Patent
1986-10-16
1988-08-09
Smith, Jerry
Excavating
371 43, G06F 1100
Patent
active
047633280
ABSTRACT:
An integrated viterbi decoder structure and method, the viterbi decoder receives test input signals at a distributor, an ACS circuit and a path memory and compares the output signals generated by the test input signals with predetermined test signals so as to test the internal operations of the viterbi decoder without the need for complex logic housed with the viterbi decoder.
REFERENCES:
patent: 4240156 (1980-12-01), Doland
patent: 4606027 (1986-08-01), Otani
patent: 4614933 (1986-09-01), Yamashita
patent: 4680761 (1987-07-01), Burkness
P. E. C. Hoppes, et al., "A Monolithic CMOS Maximum-Liklihood Convolutional Decoder", IEEE, 1982, pp. 27-29.
S. Crozier, "Microprocessor Based Implentation and Testing of a Simple Viterbi Detector", Elec. Eng., vol. 6, No. 3, 1981, pp. 3-8.
Katoh Tadayoshi
Shimoda Kaneyasu
Yamashita Atsushi
Beausoliel Robert W.
Fujitsu Limited
Smith Jerry
LandOfFree
Viterbi decoder and method for testing the viterbi decoder does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Viterbi decoder and method for testing the viterbi decoder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Viterbi decoder and method for testing the viterbi decoder will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-922910