Viterbi decoder and method for testing the viterbi decoder

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371 43, G06F 1100

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active

047633280

ABSTRACT:
An integrated viterbi decoder structure and method, the viterbi decoder receives test input signals at a distributor, an ACS circuit and a path memory and compares the output signals generated by the test input signals with predetermined test signals so as to test the internal operations of the viterbi decoder without the need for complex logic housed with the viterbi decoder.

REFERENCES:
patent: 4240156 (1980-12-01), Doland
patent: 4606027 (1986-08-01), Otani
patent: 4614933 (1986-09-01), Yamashita
patent: 4680761 (1987-07-01), Burkness
P. E. C. Hoppes, et al., "A Monolithic CMOS Maximum-Liklihood Convolutional Decoder", IEEE, 1982, pp. 27-29.
S. Crozier, "Microprocessor Based Implentation and Testing of a Simple Viterbi Detector", Elec. Eng., vol. 6, No. 3, 1981, pp. 3-8.

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