Boots – shoes – and leggings
Patent
1995-05-12
1996-03-26
Bowler, Alyssa H.
Boots, shoes, and leggings
395800, 364230, 3642318, 3642616, 364DIG1, G06F 938
Patent
active
055028276
ABSTRACT:
A data processor which is capable of executing two kinds of instructions, such as an integer operation instruction and a floating-point operation instruction, and which has bits in a PSW to control the timing of accepting an exception (FPU exception) generated when either of the instructions, such as the floating-point operation instruction, was executed, and which switches a mode that the FPU exception is either accepted at every end of the instructions or delayed until before execution of the following floating-point operation instruction, and which saves instruction addresses, operands, and the like related to the exception so as to perform effective processing of the FPU exception.
REFERENCES:
patent: 4970641 (1990-11-01), Hester et al.
patent: 5021991 (1991-06-01), MacGregor et al.
patent: 5043867 (1991-08-01), Bhandarkar et al.
patent: 5075844 (1991-12-01), Jardine et al.
patent: 5095426 (1992-03-01), Senta
patent: 5109514 (1992-04-01), Garner et al.
patent: 5134693 (1992-07-01), Saini
patent: 5193158 (1993-03-01), Kinney et al.
"i486 Microprocessor," Intel Corp. 1989.
"A 1,000,000 Transistor Microprocessor," L. Kohn, et al 1989 ISSCC Digest of Papers, pp. 54-55.
Bowler Alyssa H.
Mitsubishi Denki & Kabushiki Kaisha
Shah Alpesh M.
LandOfFree
Pipelined data processor for floating point and integer operatio does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pipelined data processor for floating point and integer operatio, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelined data processor for floating point and integer operatio will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-922790