Bus system with virtual logical buffer

Details Bus system with virtual logical buffer Bus system with virtual logical buffer

1993-02-16

1996-03-26

Auve, Glenn A.

395872, 395850, G06F 1310

Patent

active

055028233

ABSTRACT:
A bus system is disclosed in which the CPU reads program controlling data from a ROM and stores the read data into a RAM through an internal bus line. The CPU causes interrupts on the RAM at predetermined timing to thereby supply data required for controlling to such electronic units as a VTR and an LDP. With the described arrangement, no matter of what specification the communication IC used may be, the change required to be made in the related program can be reduced.

REFERENCES:
patent: 4071887 (1978-01-01), Daly et al.
patent: 4794386 (1988-12-01), Bedrij et al.
patent: 5123107 (1992-06-01), Mensch, Jr.
patent: 5208913 (1993-05-01), Yamamoto
patent: 5253060 (1993-10-01), Welmer et al.
patent: 5276807 (1994-01-01), Kodama et al.
patent: 5353415 (1994-10-01), Wolford et al.

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