Memory connected state detecting circuit

Details Memory connected state detecting circuit Memory connected state detecting circuit

1986-09-30

1989-09-12

Heckler, Thomas M.

Boots, shoes, and leggings

371 21, 36494492, 3649472, G06F 1128, G06F 704

Patent

active

048666629

ABSTRACT:
A memory connected state detecting circuit for automatically detecting the memory connected condition, comprising a timing circuit responsive to a certain operation mode signal and a clock signal for producing different timing and control signals and address information, a switching circuit for controlling the read/write operations in such a manner that each data for checking is written in each of designated addresses and it is read just after it has been written, and a latching circuit for latching the data read from the memory. With this construction, it has become possible to detect whether or not the memory capacity of an additional memory or memories mounted can sufficiently cover the memory area designated by a computer, without providing any mechanical switches and associated wiring.

REFERENCES:
patent: 3579199 (1971-05-01), Anderson et al.
patent: 3751649 (1973-08-01), Hart, Jr.
patent: 4195770 (1980-04-01), Benton et al.
patent: 4369511 (1983-01-01), Kimura et al.
patent: 4370746 (1983-01-01), Jones et al.
patent: 4450560 (1984-05-01), Conner
patent: 4601034 (1986-07-01), Sridhar
patent: 4667330 (1987-05-01), Kumagai

Affiliated with

Also associated with

Rating

Memory connected state detecting circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory connected state detecting circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory connected state detecting circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-922456