Digital multiplying circuit

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364757, 371 371, G06F 752, G06F 1110

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048666548

ABSTRACT:
A digital multiplying circuit comprises an input terminal serially applied with input vectors which are elements of a finite field GF(2.sup.h), where h is a natural number, an output terminal for producing a signal obtained by multiplying a desired multiplying constant to one input vector, and h multiplying circuit parts each comprising a multiplier and a data selector for selectively producing an input or output signal of the multiplier responsive to an external selection signal. The h multiplying circuit parts are coupled in series between the input terminal and the output terminal, and an r-th multiplier among the multipliers with the h multiplying circuit parts has a multiplying constant .alpha..sup.z, where r=1, 2, . . . , h, .alpha. is a primitive element of the finite field GF(2.sup.h) and z=2.sup.(r-1). At least one of the data selectors within the h multiplying circuit parts comprises a control terminal and is forced to produce a zero output signal responsive to an external control signal applied to the control terminal.

REFERENCES:
patent: 3668632 (1972-06-01), Oldham, III
patent: 4037093 (1985-04-01), Gregg et al.
patent: 4162480 (1979-07-01), Berlekamp
patent: 4251875 (1981-02-01), Marver et al.
patent: 4584686 (1986-04-01), Fritze
patent: 4586183 (1986-04-01), Wilkinson
Wang et al., "VLSI Architectures for Computing Multiplications and Inverses in GF(2.sup.m)", IEEE Trans. on Computers, vol. C-34, #8, pp. 709-716, Aug. 85.

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