Method and circuit arrangement for adding floating point numbers

Details Method and circuit arrangement for adding floating point numbers Method and circuit arrangement for adding floating point numbers

1987-08-26

1989-09-12

Wan, Gene

Boots, shoes, and leggings

364751, G06F 738

Patent

active

048666513

ABSTRACT:
For successively adding a series of floating point numbers, a floating point adder stage (FIG. 2) is used which, in addition to the sum of two floating point operands, emits the remainder, truncated from the smaller operand, as a floating point number. For obtaining an exact sum of the operands, these remainders are summed in the form of intermediate sums. A circuit arrangement for parallel operation comprises series-connected floating point adder stages (FIG. 6), the intermediate sum occurring at the output of each stage and the intermediate remainder being buffered. Remainders are in each case passed on to the next stage, their value decreasing until they are zero. A serially operating arrangement (FIG. 8) comprises a single adder stage (30) and a register stack (34) for buffering the intermediate sums and the final result. A remainder occurring is stored in a remainder register (32) at the output of the adder stage and added to the intermediate sums until the remainder is zero. Subsequently, a fresh operand is applied to the input of the adder stage.

REFERENCES:
patent: 4644490 (1987-02-01), Kobayashi et al.
IBM Journal of Research and Development, vol. 11, No. 1, 1/67, pp. 34-53, New York, U.S., S. F. Anderson et al.: "The IBM System/360 Model 91: Floating-point Execution Unit", FIG. 3 and text.
Communications of the ACM, vol. 14, No. 11, 11/71, pp. 731-736, New York, U.S., M. A. Malcolm: "On Accurate Floating-point Summation", paragraph: Extended Summation with Cascading Accumulators.
Communications of the ACM, vol. 7, No. 6, 6/64, pp. 355-356, New York, U.S. J. M. Wolfe: "Reducing Truncation Errors by Programming", entire document.
Mini-Micro Conference Record, 5/84, pp. 10/1(1)-10/1(10), Northeast, New York, U.S.; Nusra Lodhi et al: "System Solutions for a High-Speed Processor Using Innovative ICs", FIG. 10 and text.

Affiliated with

Also associated with

Rating

Method and circuit arrangement for adding floating point numbers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and circuit arrangement for adding floating point numbers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and circuit arrangement for adding floating point numbers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-922331