Patent
1977-02-01
1978-08-08
Safourek, Benedict V.
325421, H04L 2722
Patent
active
041059751
ABSTRACT:
An offset error correction circuit for improved reception of signals by compensating for any offset error voltage produced by a phase detector in the absence of an input signal to the detector. The error correction circuit translates the offset error voltage into a digital value and stores that value in a counter. When a PSK signal is applied to the circuit, the error correction circuit subtracts the stored value of the offset error voltage from the output of the phase detector which compensates for the offset error. The compensation for the offset error provides an improved signal to noise ratio.
REFERENCES:
patent: 3777272 (1973-12-01), Fletcher
patent: 3936758 (1976-02-01), Kostelnicek et al.
Chambers Ramon P.
Gordy Robert S.
Sanders David E.
Cavender J. T.
Dugas Edward
NCR Corporation
Safourek Benedict V.
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