Method of testing for stuck-at fault in a synchronous circuit

Details Method of testing for stuck-at fault in a synchronous circuit Method of testing for stuck-at fault in a synchronous circuit

1993-01-28

1996-03-26

Beausoliel, Jr., Robert W.

Excavating

371 27, G01R 3128

Patent

active

055027296

ABSTRACT:
The time series test pattern is generated by applying a system clock to the synchronous circuit. By expanding the synchronous circuit into a plurality of combinational circuit. The internal input to the combinational circuit is changed without applying the system clock to the synchronous circuit and the output of the combinational circuit is observed to determine whether the test pattern including the primary input enables to be detected. When the test pattern and extended test pattern are determined, they are applied to the synchronous circuit to detect a fault. The extended test pattern is formed by applying random number to the primary input and by performing a fault simulation based on the random number. The extended test pattern can be also cleared by using a conventional algorithm for finding the test pattern.

REFERENCES:
patent: 4204633 (1980-05-01), Goel
patent: 4493077 (1985-01-01), Agrawal et al.
patent: 4534028 (1985-08-01), Trischler
patent: 4601032 (1986-07-01), Robinson
patent: 4852093 (1989-07-01), Koeppe
patent: 5043985 (1991-08-01), Lin et al.
patent: 5172377 (1992-12-01), Robinson et al.

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