Semiconductor memory device with deep bit-line channel stopper

Details Semiconductor memory device with deep bit-line channel stopper Semiconductor memory device with deep bit-line channel stopper

1986-12-12

1988-08-09

Clawson, Jr., Joseph E.

357 14, 357 52, 357 89, 357 91, H01L 2978

Patent

active

047631821

ABSTRACT:
A semiconductor memory device comprises a first conductivity type semiconductor substrate (1) formed thereon with a charge storage region (5) and a second conductivity type region (6) serving as a bit line, and first conductivity type highly concentrated regions (8, 11) higher in concentration than the semiconductor substrate (1) at least by one digit are formed to enclose the charge storage region (5) and the bit line region (6) respectively. Thus, potential barriers against electrons can be defined in interfaces between the highly concentrated region (8) and the charge storage region (5) and between the highly concentrated region (11) and the bit line region (6), thereby to prevent malfunction caused by incidence of radioactive rays such as alpha rays.

REFERENCES:
patent: 4164751 (1979-08-01), Tasch
patent: 4247862 (1981-01-01), Klein
patent: 4377756 (1983-03-01), Yoshihara et al.
patent: 4467450 (1984-08-01), Kuo
patent: 4688064 (1987-08-01), Ogura et al.

Affiliated with

Also associated with

Rating

Semiconductor memory device with deep bit-line channel stopper does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with deep bit-line channel stopper, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with deep bit-line channel stopper will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-921425