Single cycle flush for RAM memory

Details Single cycle flush for RAM memory Single cycle flush for RAM memory

1994-11-30

1996-03-26

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365194, G11C 700

Patent

active

055026702

ABSTRACT:
The present invention provides methods and apparatus for resetting all of the cells in a random access memory (RAM) during one clock cycle without requiring ancillary drivers. At the start of the reset cycle, each column in the memory array is selected to receive the reset value and then each data line in the array is driven low while the inverse of the data line is driven high. After a first predetermined delay, each word line is driven high and all of the memory cells are thus reset. The word lines are then driven low and after a second predetermined delay, the data lines are driven back to a high value. In this manner, each cell in the memory array is reset during one clock cycle.

REFERENCES:
patent: 4541073 (1985-09-01), Brice et al.
patent: 4616344 (1986-10-01), Noguchi et al.
patent: 4989182 (1991-01-01), Mochizuki et al.

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