Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1988-05-03

1989-09-12

James, Andrew J.

357 6, 357 236, 357 2314, 357 41, 357 51, H01L 2978, H01L 4902, H01L 2702

Patent

active

048664936

ABSTRACT:
A sense transistor of an EEPROM has a conductive diffusion layer which is isolated from the source-drain region of the sense transistor and newly formed on the surface of the semiconductor substrate beneath the floating gate of the sense transistor. The conductive diffusion layer is connected to the control gate of the sense transistor, whereby a capacitance between the control gate and the floating gate is increased without increasing the facing area of the control gate and the floating gate.

REFERENCES:
patent: 4251829 (1981-02-01), Adam
patent: 4363109 (1982-12-01), Gardner, Jr.
"Design Consideration for Scaling Flotox E.sup.2 PROM Cell", Jimmy Lee et al., IEEE IEDM 83, pp. 589-592, 1983.
"Reliablility, Aspects of a Floating Gate E.sup.2 PROM", Bruce Euzent et al., IEEE/PROC. IRPS., pp. 11-16, 1981.
"An EEPROM for Microprocessors and Custom Logic", R. Cuppens et al., IEEE ISSCC Dig. Tech. Papers, pp. 268-269, Feb. 24, 1984.

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