Self-aligning double polycrystalline silicon etching process

Details Self-aligning double polycrystalline silicon etching process Self-aligning double polycrystalline silicon etching process

1978-06-12

1979-03-06

Massie, Jerome W.

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29571, 29578, 29580, 156628, 156653, 156657, 156661, 156662, 357 23, 357 59, H01L 2122, H01L 21308

Patent

active

041429265

ABSTRACT:
A process for fabricating a double layer polycrystalline silicon structure for a metal-oxide-semiconductor (MOS) integrated circuit. The upper polycrystalline silicon layer after being etched to form a predetermined pattern is used as a masking member for etching the lower polycrystalline silicon layer, thereby assuring alignment between the layers. A selective etchant which discriminates between the silicon layers is employed.

REFERENCES:
patent: 3721593 (1973-03-01), Hays et al.
patent: 3767494 (1972-10-01), Muroaka et al.
patent: 3817799 (1974-06-01), Schuter et al.
patent: 3897282 (1975-07-01), White
patent: 3909325 (1975-09-01), Church et al.
patent: 3940288 (1976-02-01), Takagi et al.
patent: 3996657 (1976-12-01), Simko et al.

Affiliated with

Also associated with

Rating

Self-aligning double polycrystalline silicon etching process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligning double polycrystalline silicon etching process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligning double polycrystalline silicon etching process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-919956