Method of making contact alignment for nonvolatile memory device

Details Method of making contact alignment for nonvolatile memory device Method of making contact alignment for nonvolatile memory device

1993-09-10

1994-12-27

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437193, 437978, 437979, H01L 21441

Patent

active

053765710

ABSTRACT:
A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size.

REFERENCES:
patent: 4935380 (1990-06-01), Okumura
patent: 5013674 (1991-05-01), Bergemont
patent: 5019527 (1991-05-01), Ohshima et al.
patent: 5028990 (1991-07-01), Kotaki et al.
patent: 5060190 (1991-10-01), Chen et al.
patent: 5081060 (1992-01-01), Kim
patent: 5113238 (1992-05-01), Wang et al.
patent: 5231043 (1993-07-01), Chan et al.
Wolf et al., "Silicon processing for the VLSI Era", pp. 384-387, 1986.

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