Method of fabricating polycrystalline silicon resistors having d

Details Method of fabricating polycrystalline silicon resistors having d Method of fabricating polycrystalline silicon resistors having d

1987-02-20

1988-08-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

148DIG136, 437918, 437 27, 437247, 357 59, H01L 21265

Patent

active

047628014

ABSTRACT:
A method of fabricating polycrystalline silicon resistors having nearly zero or positive temperature coefficient includes the steps of depositing a layer of polycrystalline silicon, implanting the layer with silicon to make the layer substantially amorphous, introducing an impurity to dope the layer, and annealing the layer.

REFERENCES:
patent: 4467519 (1984-08-01), Glang et al.
patent: 4579600 (1986-04-01), Shah et al.
patent: 4643777 (1987-02-01), Maeda
Ghandhi, VLSI Fabrication Principles, New York: John Wiley and Sons, Inc., 1983.
S. Prussin et al., "Formation of Amorphous Layers by Ion Implantation," J. Appl. Phys. (15 Jan. 1985) 57(2):180-185.

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