Method and a means for checking normalizing operations in a comp

Details Method and a means for checking normalizing operations in a comp Method and a means for checking normalizing operations in a comp

1982-07-13

1985-07-09

Malzahn, David H.

Boots, shoes, and leggings

364748, G06F 1100

Patent

active

045286400

ABSTRACT:
A method and a means are disclosed for the throughchecking of the normalizer operations of an arithmetic unit of a data processing system involving both integer and floating-point formats in single and double precision operations. A post normalizer is used in conjunction with the main normalizer of the arithmetic unit to determine if the result is indeed normalized. Where the post normalize count is zero, an error designator remains inactivated. However, where the count is non-zero, the error designator is activated to indicate an error exists, unless it is disabled by separate circuitry which detects that the number being shifted is .+-..0.. The preferred embodiment disclosed herein checks the operation of a pair of 72-bit main normalizers with a single 13-bit post normalizer. A plurality of instructions in which this check is significant are illustrated.

REFERENCES:
patent: 3551665 (1970-12-01), Powers et al.
patent: 3831012 (1974-08-01), Tate et al.
patent: 3871578 (1975-03-01), Van de Goor et al.
patent: 4366548 (1982-12-01), Kregness et al.

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