Computer system with high speed data transfer capabilities

Details Computer system with high speed data transfer capabilities Computer system with high speed data transfer capabilities

1989-07-10

1992-10-27

Bowler, Alyssa H.

395500, 395550, G06F 1200, G06F 1300

Patent

active

051596792

ABSTRACT:
The present invention is a computer system which can perform master unit controlled memory accesses at a first rate, DMA controlled operations at a second rate and burst operations of both types at a higher third rate. The burst operation is set up by performing a standard access cycle, thus setting up the dynamic random access memory row address, and then performing a series of fast, column address-only accesses to the same page of memory. The fast mode must be exited to a standard rate access whenever a page boundary is crossed, with burst operations recommencing thereafter. Wait states can be inserted in all type operations. Thirty-two bit master units can downshift or step down to 16 bit operation to respond to 16 bit burstable responding units.

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