Localized semiconductor substrate for multilevel transistors

Details Localized semiconductor substrate for multilevel transistors Localized semiconductor substrate for multilevel transistors

1996-10-10

1998-09-15

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257777, 257506, H01L 2976, H01L 31076, H01L 3120

Patent

active

058083197

ABSTRACT:
A dual level transistor integrated circuit and a fabrication technique for making the integrated circuit. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed upon a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate. The integrated circuit further includes a first transistor. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric. The integrated circuit further includes a first inter-substrate dielectric that is formed on the first conductive gate structure and the global substrate. A first local substrate is formed on an upper surface of the first inter-substrate dielectric. A second transistor is located within the first local substrate. The second transistor includes a second gate dielectric formed on an upper surface of the first local substrate and a second conductive gate structure formed on an upper surface of the second gate dielectric.

REFERENCES:
patent: 5006913 (1991-04-01), Sugahara et al.
patent: 5473181 (1995-12-01), Schwalke et al.

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