Programmable serial multiplier

Details Programmable serial multiplier Programmable serial multiplier

1990-12-13

1992-10-27

Malzahn, David H.

Boots, shoes, and leggings

364754, G06F 752

Patent

active

051595672

ABSTRACT:
A programmable serial multiplier performing the multiplication of a multiplicand by a fixed constant coded on r bits is formed from a battery of (r/2)-1 addition cells (11.sub.O -11(r/2)-2) interconnected in series by a first input, a shift register formed from (r/2)+1 initializable flip-flops (10.sub.O -10.sub.r /2), and an interconnection channel. The latter makes it possible to program the serial multiplier in order to perform the multiplication by the fixed constant C, either with the aid of the value +C when the constant C contains, in binary notation, a number of 1s less than or equal to the number of 0s, or with the aid of the value -C in the reverse case. It may operate with a signed fixed constant C.
A computational processor which carries out a linear transform of numerical data, implements such a multiplier. For each multiplication of the linear transform, the processor may operate either with the constant proper or with the constant's oppositely signed number. For each step of the computation, the correct result is then determined by inverting the type of operator provided for the summation operation concerned.

REFERENCES:
patent: 3456098 (1969-07-01), Gomez et al.
patent: 4839847 (1989-06-01), Laprade
patent: 4853887 (1989-08-01), Jutand et al.
patent: 5031137 (1991-07-01), Elrod

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