Nonvolatile semiconductor device with a trench isolator

Details Nonvolatile semiconductor device with a trench isolator Nonvolatile semiconductor device with a trench isolator

1991-02-13

1992-10-27

James, Andrew J.

357 233, 357 235, 357 2314, H01L 2934, H01L 2910, H01L 2968, H01L 2992

Patent

active

051594315

ABSTRACT:
A source diffusion region and a drain diffusion region are formed under an insulation film which is thicker than a gate insulation film and which isolates the adjacent channel regions from each other. The adjacent source and drain diffusion regions are isolated from each other by a trench which extends from the central portion of the thick insulation film to the interior of a semiconductor substrate. The trench is formed in a self-alignment manner with reference to the end portions of the adjacent floating gate electrodes, and the depth of this trench is determined so that the adjacent source and drain diffusion regions can be spaced sufficiently apart from each other. Since the trench reliably prevents punch-through and current leakage to the adjacent element, it is possible to remarkably reduce the cell size. Moreover, the peripheral circuits are not complicated since the functions of the source and drain regions are fixed.

REFERENCES:
patent: 4326331 (1982-04-01), Guterman
patent: 4455740 (1984-06-01), Iwai
patent: 4698900 (1987-10-01), Esquivel
patent: 4855800 (1989-08-01), Esquivel et al.
patent: 4951103 (1990-08-01), Esquivel et al.
patent: 4979004 (1990-12-01), Esquivel et al.
IEDM Technical Digest, 1986; "High Density Contactless, Self-Aligned EPROM Cell Array Technology", Equivel et al., pp. 592-595.
IEEE International Solid-State Circuits Conference, 1987; "Nonvolatile Memory-A 1Mb CMOS EPROM with a 13.5 .mu.m.sup.2 Cell", Coffman et al., pp. 72, 73 and 343.
Symposium On VLSI Technology Digest of Technical Papers, May 21, 1987; "Shallow Trench Isolated Buried N+ FAMOS Transistors For VLSI EPROMs", Esquivel et al., pp. 105 and 106.
IEDM Technical Digest, 1987; "A New Self-Aligned Planar Array Cell For Ultra High Density EPROMs", Mitchell et al., pp. 548-551.

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