Semiconductor device having short channel field effect transisto

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357 231, 357 233, 357 41, H01L 2978

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active

051594170

ABSTRACT:
A semiconductor device comprises a semiconductor substrate (1), a source region (5) and a drain region (6) a first gate electrode (4), a second gate electrode (8), an insulator layer (9) and a conductor layer (10). The semiconductor substrate (1) contains impurity of a first conductive type in a predetermined concentration. The source region (5) and the drain region (6) are formed and spaced on the main surface of the semiconductor substrate (1), and contains impurity of a second conductive type in a concentration which is 10 to 10.sup.3 times as large as that of the impurity of the first conductive type. The first gate electrode (4) is located between the source and drain regions (5) and (6) and formed on the main surface of the semiconductor substrate (1) with an insulating film (3) therebetween. The second gate electrode (8) is formed to have portions overlapping a portion of the source region (5) and a portion of the first gate electrode (4) with an insulating film (7 ) therebetween. The insulator layer (9) has an opening (20) through which surfaces of at least the first and second gate electrodes (4) and (8) are exposed. The conductor layer (10) electrically contacts the surfaces of the first and second gate electrodes (4) and (8) through the opening (20). The field effect transistor has a high current drive capacity and a high resistance to the hot carriers. The field effect transistor can have a gate length of a quarter micron order.

REFERENCES:
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patent: 4642881 (1987-02-01), Matsukawa et al.
patent: 4868617 (1989-09-01), Chiao et al.
patent: 4907041 (1990-03-01), Huang
IEEE Electron Device Letters, vol. 11, No. 2, Feb. 1990, "Simple Gate-to-Drain Overlapped MOSFET's Using Poly Spacers for High Immunity to Channel Hot-Electron Degradation" by Chen et al, pp. 78-81.
IBM Technical Disclosure Bulletin, vol. 30, No. 12, May 1988, "Simplified Lightyly Doped Drain Process", p. 180-181.
"The Impact of Gate-Drain Overlapped LDD (GOLD) for Deep Submicron VLSI's", IEDM Tech. Dig., 1987, pp. 38-41, Izawa et al.
"High Dielectric LDD Spacer Technology for High Performance MOSFET Using Gate-Fringing Field Effects", IEDM Tech. Dig., 1989, pp. 613-616, Mizuno et al.

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