Radiation hardened-self aligned CMOS and method of fabrication

Details Radiation hardened-self aligned CMOS and method of fabrication Radiation hardened-self aligned CMOS and method of fabrication

1980-09-25

1983-08-30

James, Andrew J.

357 67, 357 91, 357 65, H01L 2702, H01L 2348, H01L 2946

Patent

active

044020023

ABSTRACT:
A radiation hardened CMOS formed by applying a radiation hard gate oxide layer on a silicon substrate, applying silicon doped aluminum gates on the gate oxide, and by ion implanting and annealing source and drain regions using said gates as masks at a temperature of or below 500 degrees centigrade. Using an N.sup.- type substrate, a P.sup.+ guard ring is formed at the interface of the P.sup.- well of the N channel MOS device and the N.sup.- substrate before the formation of the gate oxide.

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