Integrated digital multiplier circuit using current mode logic

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307216, 364784, G06F 750, G06F 752

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active

042154189

ABSTRACT:
A parallel digital multiplier circuit fabricated in accordance with an advanced triple diffusion process providing feature geometry down to a minimum of two microns and junction depths of less than two microns, wherein a high packing density provided by the fabrication process is utilized to full advantage by the use of current mode logic, which requires relatively few and relatively small resistors, uses only inherently faster NPN transistors, employs a relatively small voltage swing between logic levels, has unlimited cascading capability, and provides a superior speed-power product.

REFERENCES:
patent: 3519810 (1970-07-01), Priel et al.
patent: 3900724 (1975-08-01), McIver et al.
patent: 4071904 (1978-01-01), Miller

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