Multi-stage, integrated decoder device having redundancy test en

Details Multi-stage, integrated decoder device having redundancy test en Multi-stage, integrated decoder device having redundancy test en

1988-03-16

1989-08-08

Hudspeth, David

Excavating

307441, 307463, 307243, 307449, 36523006, 371 10, H03K 19003

Patent

active

048556211

ABSTRACT:
A multi-stage, integrated decoder device includes a special function which facilitates the simultaneous activation of a plurality or as many as all of its outputs while gating out a pre-selectible output. When used as bit line decoder, it is thus possible to activate a plurality or up all of the bit lines (including any redundancy bit lines) of a block of storage cells of a semiconductor memory, excluding a bit line assumed to contain at least one defective storage cell.

REFERENCES:
patent: 4194130 (1980-03-01), Moench
patent: 4309629 (1982-01-01), Kamuno
patent: 4584674 (1986-04-01), Watanabe
patent: 4635232 (1987-01-01), Iwahashi et al.
patent: 4635233 (1987-01-01), Matsumoto et al.
patent: 4672240 (1987-06-01), Smith et al.
patent: 4691300 (1987-09-01), Pelley, III et al.
patent: 4720817 (1988-01-01), Childers
patent: 4721868 (1988-01-01), Cornell et al.
patent: 4733394 (1988-03-01), Giebel
"High Performance Complementary Decoder/Driver Circuit", IBM T.D.B., vol. 29, No. 6, 11-1986, pp. 2390-2394.

Affiliated with

Also associated with

Rating

Multi-stage, integrated decoder device having redundancy test en does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-stage, integrated decoder device having redundancy test en, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-stage, integrated decoder device having redundancy test en will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-907941