MOS Decoder circuit

Details MOS Decoder circuit MOS Decoder circuit

1980-09-04

1983-08-30

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307463, H03K 19094

Patent

active

044019033

ABSTRACT:
An MOS decoder circuit including parallel rows or columns of MOS transistors connected to an input signal to be decoded. Two clocked MOS transistors of a channel type different from that used to form the rows of MOS transistors are connected as load resistances, one being connected to the drains of one row of transistors and the other being connected to an MOS transistor circuit coupled to another row of MOS transistors.

REFERENCES:
patent: 3965369 (1976-06-01), Hatsukano
patent: 4063118 (1977-12-01), Nishimura
Stewart, High Density CMOS ROM Arrays, 1977 IEEE International Solid-State Circuits Conference, pp. 20-21, 230, (Feb. 16, 1977).
Akiya and Ohara, New Input/Output Designs for High Speed Static CMOS RAM, IEEE Journal of Solid-State Circuits, vol. SC-14, No. 5, pp. 823-828, (Oct. 1979).

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