Patent
1996-05-16
1999-07-06
An, Meng-Ai T.
395385, 395386, 395568, 395376, G06F 942, G06F 930
Patent
active
059207132
ABSTRACT:
An instruction decoder includes an emulation code sequencer and emulation code ROM for handling various instructions. The emulation code ROM includes a sequence of operations (Op) and an operation sequencing control code (OpSeq). Branch instructions such as conditional branch instructions may be encoded into the emulation code ROM so that a second branch, in combination with the branching operation controlled by the OpSeq code, is applied to an operation code sequence. Two-way branching permits flexible branching to locations within the emulation code ROM so that memory capacity is conserved. A superscalar microprocessor includes an instruction decoder having an emulation code control circuit and an emulation ROM which emulates the function of a logic instruction decoder. The emulation code ROM is arranged as a matrix of multiple-operation (Op) units with each multiple-Op unit including a control field that points to a next location in the emulation code ROM. In one embodiment, the emulation code ROM is arranged to include a plurality of four-Op units, called Op quads, with each Op quad including a sequencing control field, called an OpSeq field.
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Advanced Micro Devices , Inc.
An Meng-Ai T.
Koestner Ken J.
Patel Gautam R.
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