Emulation system having multiple emulator clock cycles per emula

Details Emulation system having multiple emulator clock cycles per emula Emulation system having multiple emulator clock cycles per emula

1996-11-12

1999-07-06

Teska, Kevin J.

Boots, shoes, and leggings

3642323, 3642643, 364270, 3642819, 364DIG1, G06F 11267, G06F 15177, G06F 9455

Patent

active

059207124

ABSTRACT:
An emulator system allowing a single cycle in a system clock in a user circuit to be emulated in multiple cycles of the emulator system clock. The emulator system provides a unique architecture permitting gates in the emulator to be used to emulate functions in the user circuit without requiring a fixed correspondence between a gate in the emulator and a gate in the user circuit. The emulator system operates in synchronous and asynchronous clock modes and allows the user system clock to be stopped during emulation in selected modes while still maintaining accurate emulation.

REFERENCES:
patent: 3955180 (1976-05-01), Hirtle
patent: 4306286 (1981-12-01), Cocke et al.
patent: 4357678 (1982-11-01), Davis
patent: 4527249 (1985-07-01), Van Brunt
patent: 4583169 (1986-04-01), Cooledge
patent: 4587625 (1986-05-01), Marino et al.
patent: 4656580 (1987-04-01), Hitchcock, Sr. et al.
patent: 4695968 (1987-09-01), Sullivan, II et al.
patent: 4697241 (1987-09-01), Lavi
patent: 4725971 (1988-02-01), Doshi et al.
patent: 4769817 (1988-09-01), Krohn et al.
patent: 4782461 (1988-11-01), Mick et al.
patent: 4787061 (1988-11-01), Nei et al.
patent: 4787062 (1988-11-01), Nei et al.
patent: 4819150 (1989-04-01), Jennings et al.
patent: 4862347 (1989-08-01), Rudy
patent: 4879646 (1989-11-01), Iwasaki et al.
patent: 4914612 (1990-04-01), Beece et al.
patent: 4972334 (1990-11-01), Yamabe et al.
patent: 5031129 (1991-07-01), Powell et al.
patent: 5036473 (1991-07-01), Butts et al.
patent: 5068812 (1991-11-01), Schaefer et al.
patent: 5084824 (1992-01-01), Lam et al.
patent: 5109353 (1992-04-01), Sample et al.
patent: 5114353 (1992-05-01), Sample
patent: 5126966 (1992-06-01), Hafeman et al.
patent: 5259006 (1993-11-01), Price et al.
patent: 5321828 (1994-06-01), Phillips et al.
patent: 5329470 (1994-07-01), Sample et al.
patent: 5329471 (1994-07-01), Swoboda et al.
patent: 5331571 (1994-07-01), Aronoff et al.
patent: 5345580 (1994-09-01), Tamaru et al.
patent: 5352123 (1994-10-01), Sample et al.
patent: 5377123 (1994-12-01), Hyman
patent: 5386550 (1995-01-01), Yumioka et al.
patent: 5396498 (1995-03-01), Lestral et al.
patent: 5425036 (1995-06-01), Liu et al.
patent: 5437037 (1995-07-01), Furuichi
patent: 5448496 (1995-09-01), Butts et al.
patent: 5448522 (1995-09-01), Huang
patent: 5452231 (1995-09-01), Butts et al.
patent: 5452239 (1995-09-01), Dai et al.
patent: 5475624 (1995-12-01), West
patent: 5475830 (1995-12-01), Chen et al.
patent: 5477475 (1995-12-01), Sample et al.
patent: 5551013 (1996-08-01), Beausoleil et al.
patent: 5572710 (1996-11-01), Asano et al.
M. McFarland et al., "The High-Level Synthesis of Digital Systems," IEEE, 1990 vol. 78, No. 2, pp. 301-316.
"Virtual Wires Published Papers", URL, http:/cag-www.lcs.mit.edu/vwires/papers/index.html, Mar. 26, 1997.
VHDL Mixed-Levl Fault Simulator, URL, http://www.ikos.com/products/voyagerfs/index.html, Mar. 26, 1997.
VirtualLogic SLI Emulation System, VirtualLogic SLI:, URL, http://www.ikos.com/products/vsli, Mar. 26, 1997.
"Logic Emulation for the Masses Arrives", URL,http://www.ikos.com/company
ews/pr960916.html, Mar. 26, 1997.
"Ikos Systems to Acquire Virtual Machine Works", http://www.ikos.com/company
ews/pr960311.html, Mar. 26, 1997.
Agarwal, Anant, "Virtual Wires TM A Technology for Massive Multi-FPGA systems", Virtual Machine Works (no publication date given).
Goering, R., "Emulation for the Masses", Electronic Engineering Times, Jan. 29, 1996, p. 63.
Sim Express Specifications, Mentor Graphics, Sim Express Hardware Emulator.
Maliniak, L., "Pin Multiplexing Yields Low-Cost Logic Emulation", Jan. 22, 1996.

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