Method of making vertical PNP transistor in merged bipolar/CMOS

Details Method of making vertical PNP transistor in merged bipolar/CMOS Method of making vertical PNP transistor in merged bipolar/CMOS

1987-07-02

1989-08-08

Roy, Upendra

Fishing, trapping, and vermin destroying

357 34, 357 42, 357 91, 437 34, 437 54, 437 55, 437 56, H01L 21265, B01J 1700

Patent

active

048552445

ABSTRACT:
A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer (52d) and into a base region (54c). The base region (54c) is formed in the same processing step as the N well region (54b) of the PMOS transistor (42) and the collection region (54a) of the NPN transistor (40). By diffusing into the base region (54c), the width between the collector (84) and emitter (64e) is reduced. The emitter (64e) can be formed in conjunction with the source and drain regions of the PMOS transistor (42). The vertical PNP transistor (46) is laterally isolated from the other transistor devices by an annular ring formed from an N+ region (50c) formed in conjunction with an N+ DUF region (50a) used in the NPN transistor (40), and a N+ region (56b) formed in conjunction with an N+ collector region (56a) of the NPN transistor (40). An N+ DUF region (50b) may also be used in conjunction with the PMOS transistor (42).

REFERENCES:
patent: 4403395 (1983-09-01), Curran
patent: 4484388 (1984-11-01), Iwasaki
patent: 4507847 (1985-04-01), Sullivan
patent: 4624046 (1986-11-01), Shideler et al.
patent: 4641419 (1987-02-01), Kudo
patent: 4717686 (1988-01-01), Jacobs et al.
patent: 4721684 (1988-01-01), Musumeci
Gray et al., "Analysis and Design of Analog Integrated Circuits", John Wiley & Sons, 1977, pp. 91-99.
J. Lapham et al., "A Complementary Bipolar Process for High Speed Precision Linear Circuits", pub. in Proceedings of the 1986 Bipolar Circuits and Technology Meeting, IEEE, Sep. 11-12, 1986, pp. 31-32.

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