Multiple error detection in error detection correction circuits

Details Multiple error detection in error detection correction circuits Multiple error detection in error detection correction circuits

1996-03-11

1999-07-06

Grant, William

Excavating

371 372, 371 374, 371 378, 371 3711, 39518216, G11C 2900

Patent

active

059205806

ABSTRACT:
A multi-error detector uses single byte error correcting-double byte error detecting codes but detects some multiple errors including double, triple, quadruple and more errors in a code. To detect the multiple errors, the multi-error detectors uses error pointer and a syndrome which are generated by error correction circuitry. Multiple errors are indicated when the syndrome indicates an error and either none or more than one of the error pointers are set. In one embodiment, a tree of half adders has least significant output bits from the adders coupled to input terminals of subsequent adders in the tree. Circuit logic detects multiple errors from the least significant output bit of the last adder in the tree and the more significant output bits from all the adders.

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