Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1998-02-25

1999-07-06

Le, Vu A.

Static information storage and retrieval

Floating gate

Particular biasing

36518519, 36518529, G11C 700

Patent

active

059205083

ABSTRACT:
A semiconductor memory device comprises a memory cell array comprising a plurality of nonvolatile memory cells each having a two-layer gate structure in which a floating gate and a control gate are stacked, and an auto-program/auto-erase control circuit for designating, on the basis of an erase command input, the plurality of memory cells in the memory cell array, in which data is to be erased, and automatically controlling a process, wherein the auto-program/auto-erase control circuit performs a program verify operation of a pre-program operation, repeats program and program verify operations until the program operation is completed, if the pre-program operation is necessary as a result of the program verify operation, performs erase verify operation at a time the pre-program operation is completed, and then repeats erase and erase verify operations until the erase operation is completed.

REFERENCES:
patent: 5053990 (1991-10-01), Kreifels et al.
patent: 5200920 (1993-04-01), Norman et al.
Koichi Seki et al; Non-Volatile and Fast Static Memories; An 80ns 1Mb Flash Memory with On-Chip Erase/Erase-Verify Controller; ISSCC 1990 Digest of Technical Papers, pp. 60-61.

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