Method for lubricating a high capacity dram cell

Details Method for lubricating a high capacity dram cell Method for lubricating a high capacity dram cell

1986-09-25

1989-05-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 38, 437 48, 437 51, 437 52, 437 60, 437203, 437 79, 437919, H01L 21225

Patent

active

048290173

ABSTRACT:
A dynamic random access memory cell (14) is disclosed which is characterized by a high capacity storage element and small lateral wafer area. The cell (14) is constructed with a word line (40) overlying a split bit line (48, 50), with an underlying transistor 30, and yet thereunder a high capacitance capacitor (34). The word line (40) includes a member (42) isolated from the bit line (36) and formed therethrough to provide the transistor gate conductor. The transistor gate insulator (44) covers the gate conductor (42), and is encircled by a transistor semiconductor region (46) forming a vertical transistor conduction channel. The split bit line elements (48, 50) are in electrical contact with an underlying transistor drain region (126). The transistor conduction channel (46) is also in contact with an underlying transistor source region forming one plate (52) of the capacitor (34). The capacitor plate (52) is a core which is enclosed annularly by dielectric isolation (54). Another semiconductor capacitor plate (56) encircles the dielectric isolation (54).

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