Address translation unit

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Details

G06F 932, G06F 936

Patent

active

048129690

ABSTRACT:
An address translation unit for use in a computer system having a multi-virtual space comprises a full associative translation lookaside buffer (TLB) which includes, for each entry, an associative memory array which stores and compares addresses. The associative memory array is provided with a circuit which, when a specific value is set in a common area field, invalidates comparison in a space number field.

REFERENCES:
patent: 4068303 (1978-01-01), Morita
patent: 4376297 (1983-03-01), Anderson et al.
patent: 4453230 (1984-06-01), Mizoguchi et al.
patent: 4456954 (1984-06-01), Bullions et al.
patent: 4551797 (1985-11-01), Amdahl et al.
patent: 4612612 (1986-09-01), Woffinden et al.
patent: 4733350 (1988-03-01), Tone et al.

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