System for DMA controller sharing control signals in conventiona

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G06F 1320

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active

058389938

ABSTRACT:
A distributed direct memory access (DMA) architecture where DMA controllers are modified to create isolated DMA channels. Each isolated channel includes its own set of uniquely addressable registers which provide functional compatibility with conventional DMA controllers. A DMA master interacts compatibly with the computer system and transparently communicates special cycles to the isolated DMA channels to cause the distributed DMA architecture to appear as the DMA controllers. The DMA master spawns special cycles to the isolated channels for sharing common write data with multiple channels and merging read data into a single DMA controller compatible register. Channel 4 cascading is also handled via tracking registers and special cycles to maintain disable and masking functionality of channel 4 as it effects channels 0-3.

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patent: 5608889 (1997-03-01), Werlinger et al.
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patent: 5673400 (1997-09-01), Kenny
patent: 5685012 (1997-11-01), Klein
Intel.RTM. 8237A High Performance Programmable DMA Controller (8237A, 8237A-4, 8237A-5); Oct. 1987 (pp. 2-222--2-258).
PCI, Revision 2.1, A100910-940 (pp. 35-55); Jun. 1, 1995.
DMA Support on the "PCIway", Aug. 2, 1995, Version 5.4, Preliminary, pp. 2-16.

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