Planar doped barrier gate field effect transistor

Details Planar doped barrier gate field effect transistor Planar doped barrier gate field effect transistor

1981-11-23

1984-04-10

James, Andrew J.

357 58, 357 89, 357 4, H01L 2980, H01L 2912, H01L 2712

Patent

active

044424450

ABSTRACT:
Disclosed is an epitaxial layer field effect transistor having a planar dd barrier gate formed on an n-type semiconductor planar channel region between drain and source terminals formed on the surface of the channel region. The semiconductor channel region is fabricated on a semiconductor substrate, preferably GaAs and being separated therefrom by one or more semiconductor planar buffer regions. The planar doped barrier gate comprises an n.sup.+ -.pi.-p.sup.+ -.pi. structure grown by molecular beam epitaxy over the n-type channel region. Application of an electrical potential to the gate modulates the channel charge depletion in the semiconductor channel region underlying the gate causing a variation in the channel conductance laterally between the source and drain terminals.

REFERENCES:
patent: 3984858 (1976-10-01), Cornu et al.
patent: 3986192 (1976-10-01), DiLorenzo et al.
patent: 4075651 (1978-02-01), James
patent: 4083062 (1978-04-01), Ohuchi et al.
patent: 4201604 (1980-05-01), Bierig et al.

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