Method of operation and apparatus for optimizing execution of sh

Details Method of operation and apparatus for optimizing execution of sh Method of operation and apparatus for optimizing execution of sh

1996-10-01

1998-11-17

Lall, Parshotam S.

395581, G06F 938

Patent

active

058389610

ABSTRACT:
A technique for speeding CPU operations in handling branch instructions in which the target instructions is a short displacement away from its branch instruction is disclosed. When the target instruction is displaced within a predetermined number of instructions away, a logic block and counter issue an invalidating control signal which invalidates the execution of the branch instruction and instructions between the branch instruction and the target instruction. The invalidating control signal is removed when the target instruction is reached. Time is saved if the latency of the computer system is longer than the time required to cycle the instruction queue to the target instruction.

REFERENCES:
patent: 4755935 (1988-07-01), Davis et al.
patent: 5121488 (1992-06-01), Ngai
patent: 5581719 (1996-12-01), Steely, Jr. et al.
patent: 5590296 (1996-12-01), Matsuo
patent: 5734881 (1998-03-01), White et al.

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