Logic circuit connecting input and output signal leads

Details Logic circuit connecting input and output signal leads Logic circuit connecting input and output signal leads

1987-05-19

1989-03-14

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307450, H03K 19094

Patent

active

048126837

ABSTRACT:
This invention discloses a logic circuit including first, second and third transistors with the control terminals of two of those transistors being connected to the input signal lead, with the output signal lead being connected to one of the current handling terminals of one of those transistors, and with a load device connected to the respective current handling terminals of those two transistors and one of the voltage supply terminals.

REFERENCES:
patent: 4394589 (1983-07-01), Pham et al.
patent: 4410815 (1983-10-01), Ransom et al.
patent: 4491747 (1985-01-01), Shimizu
patent: 4514649 (1985-04-01), Nuzillat et al.
patent: 4575821 (1986-03-01), Eden et al.
patent: 4663543 (1987-05-01), Sitch
patent: 4698524 (1987-10-01), Plagens
patent: 4712023 (1987-12-01), Otsuki et al.
Zulecg et al, "Femtojoule High-Speed Planar GaAs E-JFET Logic", IEEE TELD, vol. ED-25, No. 6, 6-1978, pp. 628-639.

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