Tunable software control of harvard architecture cache memories

Details Tunable software control of harvard architecture cache memories Tunable software control of harvard architecture cache memories

1997-10-17

1998-11-17

Eng, David Y.

G06F 922

Patent

active

058389458

ABSTRACT:
Disclosed is an instruction-level method and system for prefetching data or instructions of variable size to specified cache sets. A prefetch instruction containing binary fields allows the compiler, loader or runtime software to control cache prefetching and reduce thrashing by providing the prefetch hardware with information as to the optimal cache set location and the optimal amount of data to be prefetched. Support of Harvard architectures with separate instruction and data caches is provided by separate software control of instruction and data caches. The cache set number is identified to indicate into which set the information is to be preloaded. The size field provides a variable prefetch size. An address field indicates the address where prefetching begins.

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