Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material
Patent
1996-10-15
1999-07-27
Dutton, Brian
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
438758, 118728, 361234, H01L 2120, H01L 2131, H01L 21469, C23C 1600
Patent
active
059306610
ABSTRACT:
A clamp for fixturing a substrate when forming and thermal processing upon the substrate a thermally flowable layer. The clamp is formed from a backing member connected to a top member through a mechanical means. The backing member and the top member are sized such that a substrate may be clamped between the backing member and the top member. A portion of the top member overlaps the substrate and leaves exposed a first portion of the substrate when the substrate is clamped between the backing member and the top member. The top member has a cross-sectional profile such that a thermally flowable layer residue formed upon the top member when a thermally flowable layer is formed upon the substrate will not flow from the top member and bridge to the thermally flowable layer when the thermally flowable layer is thermally processed.
REFERENCES:
patent: 5460703 (1995-10-01), Nulman et al.
patent: 5534110 (1996-07-01), Lenz et al.
S. Wolf et al, "Silicon Processing for the VLSI Era--vol. 1", Lattice Press, Sunset Beach, CA, 1986, pp. 359-363.
Ono et al, "Development of a Planarized Al--Si Contact Filling Technology", 1990 VMIC Conference Proceedings, Jun. 12-13, 1990, pp. 76-82.
Chen et al, "Planarized Aluminum Metallization for Sub-0.5.mu.m CMOS Technology" IEEE IEDM 90, pp. 90-51 to 90-53, 1990.
Park et al. "Al-PLAPH (ALuminum PLAnarization by Post Heating) Process for Planarized Double Metal CMOS Applications" 1991 Conference Proceedings (Jun. 11-12, 1991) pp. 326-328.
Ackerman Stephen B.
Dutton Brian
Saile George O.
Szecsy Alek P.
Vanguard International Semiconductor Corporation
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