Patent
1997-02-13
1999-07-27
Donaghue, Larry D.
395393, 395388, G06F 1500, G06F 600
Patent
active
059305207
ABSTRACT:
A parallel processing apparatus of a superscalar type includes an instruction decoding stage which decodes four instructions simultaneously fetched from an instruction memory and issues instructions which allows simultaneous execution to related function units. The instruction decoding stage includes an instruction decoder which decodes the instruction and issues the instructions allowing simultaneous execution to the function units, and a queue which queues and stores the instructions fetched from the instruction memory. This instruction decoding stage also includes a scope logic which forms a read queue address for reading the instructions of the queue in accordance with the number of issued instructions in the instruction decoder and whether a branch is generated by a branch instruction, and a queue top logic which forms a write address in the queue in accordance with a storage state of an unissued available instruction in the queue. Instructions are read from four successive addresses starting from the read address. Fetched instructions are stored in four addresses in the queue starting from the write address. Four instructions to be decoded are always supplied to the instruction decoder in accordance with an issue state of the instructions. Four instructions are always fetched from the instruction memory and queued. Therefore, the instructions can be efficiently supplied to the instruction decoder in accordance with the execution state of the instructions.
REFERENCES:
patent: 3665422 (1972-05-01), McCoy et al.
patent: 3727196 (1973-04-01), McKenny
patent: 3953838 (1976-04-01), Gilberg et al.
patent: 4295193 (1981-10-01), Pomerene
patent: 4374428 (1983-02-01), Barnes
patent: 4423482 (1983-12-01), Hargrove et al.
patent: 4476525 (1984-10-01), Ishii
patent: 4521851 (1985-06-01), Trubisky et al.
patent: 4591971 (1986-05-01), Darlington et al.
patent: 4837678 (1989-06-01), Culler et al.
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4864543 (1989-09-01), Ward et al.
patent: 4907198 (1990-03-01), Arima
patent: 4924376 (1990-05-01), Yasushi Ooi
patent: 4942525 (1990-07-01), Shintani et al.
patent: 4967343 (1990-10-01), Ngai et al.
patent: 5036454 (1991-07-01), Rau et al.
patent: 5136697 (1992-08-01), Johnson
patent: 5150468 (1992-09-01), Staplin et al.
patent: 5185868 (1993-02-01), Tran
patent: 5202967 (1993-04-01), Matsuzaki et al.
patent: 5214763 (1993-05-01), Blaner et al.
patent: 5233694 (1993-08-01), Hotta et al.
patent: 5251306 (1993-10-01), Tran
patent: 5295249 (1994-03-01), Blaner et al.
patent: 5303356 (1994-04-01), Vassiliadis et al.
Minagawa et al. "Predecoding Mechanism For SuperScaler Architecture" May 1991.
Grohoski, "Machine Organization of the IBM RISC System/6000 Processor", IBM J. Res. Develop., vol. 34, No. 1, (Jan. 1990), pp. 37-58.
Groves et al, "An IBM Second Generation RISC Processor Architecture" Proceedings of the 35th Compcon, IEEE 1990, pp. 162-170.
S. McGeady, "The 1960CA SuperScalar Implementation of the 80960 Architecture", Proceedings of the 35th Compson, IEEE 1990, pp. 232-240.
Microsoft Press Computer Dictionary copyright 1994.
Donaghue Larry D.
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Pipelining device in a parallel processing apparatus and an inst does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pipelining device in a parallel processing apparatus and an inst, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelining device in a parallel processing apparatus and an inst will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-890418