Method of testing interconnections between integrated circuits i

Details Method of testing interconnections between integrated circuits i Method of testing interconnections between integrated circuits i

1996-09-16

1998-10-06

Beausoliel, Jr., Robert W.

Excavating

371 223, 39518309, H04B 1700

Patent

active

058190252

ABSTRACT:
A method of testing the interconnections between integrated circuits in a circuit uses latches, respectively connected to the terminals of the integrated circuit, which are connectable in series as a shift register so that a test pattern of bits can be entered into the latches. The pattern of bits is transmitted through the interconnections to other latches and then shifted out of the circuit along the shift register. Discrepancies between the input and output patterns indicate malfunctioning interconnections. The method is extended to apply to a microprocessor in the circuit, the microprocessor having a program that enables it to use its RAM to act as the latches of the other integrated circuits. The program may be stored in on-chip memory in the microprocessor and where that memory is RAM. EPROM or EEPROM it may be erased therefrom after successful testing of the circuit.

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