High speed programmable divider

Details High speed programmable divider High speed programmable divider

1988-12-19

1990-12-04

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

With programmable counter

377 44, 377 48, 377110, 377116, 377119, H03K 2366, H03K 2368, H03K 2110, H03K 2138

Patent

active

049759310

ABSTRACT:
A programmable counter or frequency divider includes the combination of a fixed modulus prescaler (110) and a programmable divider (120, 130, 140, 150, 160) in which the prescaler provides more than a single clock phase to the programmable divider and the programmable divider utilizes the multiple clock phases to allow operation in a true fractional-integer mode. The overall combination of the prescaler and programmable divider functions as a programmable divider for which the minimum increment in the overall divider modulus is less than the prescaler modulus, but the maximum clock frequency usable is the maximum clock frequency of the prescaler.

REFERENCES:
patent: 3873815 (1975-03-01), Summers
patent: 3959737 (1976-05-01), Tanis
patent: 4017719 (1977-04-01), Kaplan et al.
patent: 4193037 (1980-03-01), Kyu
patent: 4555793 (1985-11-01), Benamy
patent: 4633194 (1986-12-01), Kikuchi et al.
patent: 4658406 (1987-04-01), Pappao
patent: 4773031 (1988-09-01), Tobin
patent: 4807266 (1989-02-01), Taylor
patent: 4809221 (1989-02-01), Magliocco et al.
patent: 4837721 (1989-06-01), Carmichael et al.
patent: 4856032 (1989-08-01), Klekotka et al.

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